In the field of a NAND flash memory, a stacked memory that can attain high integration without being limited by the limit of resolution of the lithography technique attracts attention. For example, a nonvolatile semiconductor memory device is proposed that has structure in which memory strings, which are formed by arranging a plurality of flat-shaped electrodes at predetermined intervals in a height direction to cross columnar semiconductor films having insulating films as charge storage layers formed to cover sides, are two-dimensionally arranged in a matrix shape and the flat-shaped electrodes are shared among the memory strings adjacent to one another in a first direction (see, for example, Japanese Patent Application Laid-Open No. 2008-171918).
In recent years, to improve characteristics of such a stacked memory, a nonvolatile semiconductor memory device is proposed in which bottoms of two memory strings adjacent to each other in a second direction orthogonal to a first direction are connected by a semiconductor layer (see, for example, Japanese Patent Application Laid-Open No. 2009-146954).
Such a nonvolatile semiconductor memory device is manufactured as explained below. First, a polysilicon film is formed above a semiconductor substrate, on which a peripheral circuit is formed, via an insulating film. A silicon oxide film and a polysilicon film to be the flat-shaped electrodes are alternately deposited on the polysilicon film. Subsequently, a U-shaped hole is formed in a memory string forming position. The insulating films as the charge storage layers are formed to cover inner walls of the U-shaped hole. Amorphous silicon layers are formed on the insulating films. Heat treatment is performed to crystallize the amorphous silicon layers and form polysilicon layers, whereby a U-shaped semiconductor layer to be a channel is formed in the U-shaped hole. Consequently, the nonvolatile semiconductor memory device in which the bottoms of the two memory strings are connected by the semiconductor layer is obtained.
In the method explained in Japanese Patent Application Laid-Open No. 2009-146954, the U-shaped semiconductor layer to be a channel is formed of polycrystal. Therefore, resistance essentially rises compared with that of a single-crystal semiconductor material and a high value cannot be realized as electric current flowing to the channel. Therefore, it is desirable that the semiconductor layer forming the channel is formed of single-crystal.
In the past, it is known that a single-crystalline germanium film is obtained by, after forming a linear polycrystal silicon film in a part on a quartz substrate and forming a linear germanium film to cross the polycrystal silicon film on the quartz substrate, performing annealing at temperature for melting the germanium film (see, for example, Masanobu Miyao, Kaoru Toko, Takanori Tanaka and Taizo Sadoh, High-quality single-crystal Ge stripes on quartz substrate by rapid-melting-growth, Applied Physics Letters, vol. 95, 022115 (2009)).
In the technology described in Masanobu Miyao, et al., the wire-like germanium film formed on a substrate plane is single-crystallized. However, the U-shaped semiconductor layer forming the channel cannot be single-crystallized by applying this manufacturing method to Japanese Patent Application Laid-Open No. 2009-146954. This is because a region functioning as a seed is necessary to form single-crystal and, as explained above, the charge storage layers are formed in the U-shaped hole and there is no region functioning as the seed for single-crystallizing the U-shaped semiconductor layer.